Métrologie électrique basse fréquence et radiofréquence appliquée aux circuits 3D empilés
Laboratoire National de Métrologie et d’Essais LNE, France
a Djamel Allal: email@example.com
This paper presents the work carried out at LNE in the framework of an EMPIR Joint Research Project “Metrology for manufacturing 3D stacked integrated circuits” in order to develop traceable measurement capabilities for structural and chemical defects inspection in high aspect ratio through silicon vias and wafer/chip bonding and thinning and accurate measurement techniques for thermal and electrical materials characterisation at the nanoscale of the vias in 3D stacked electronic circuits. Apart from coordinating the project, LNE is participating technically in the field of electrical metrology where different techniques in the low frequency and radiofrequency ranges are applied to characterize the vias in terms of resistivity and RF losses.
© The Authors, published by EDP Sciences, 2017
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.